x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately, the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too early and creates a window where the guest can re-establish the read/write mapping before writeability is prohibited.

The remote host is affected by the vulnerability described in GLSA-202208-23 (Xen: Multiple Vulnerabilities)

  - IOMMU page mapping issues on x86 T[his CNA information record relates to multiple CVEs; the text explains     which aspects/vulnerabilities correspond to which CVE.] Both AMD and Intel allow ACPI tables to specify     regions of memory which should be left untranslated, which typically means these addresses should pass the     translation phase unaltered. While these are typically device specific ACPI properties, they can also be     specified to apply to a range of devices, or even all devices. On all systems with such regions Xen failed     to prevent guests from undoing/replacing such mappings (CVE-2021-28694). On AMD systems, where a     discontinuous range is specified by firmware, the supposedly-excluded middle range will also be identity-     mapped (CVE-2021-28695). Further, on AMD systems, upon de-assigment of a physical device from a guest, the     identity mappings would be left in place, allowing a guest continued access to ranges of memory which it     shouldn't have access to anymore (CVE-2021-28696). (CVE-2021-28694, CVE-2021-28695, CVE-2021-28696)

  - grant table v2 status pages may remain accessible after de-allocation Guest get permitted access to     certain Xen-owned pages of memory. The majority of such pages remain allocated / associated with a guest     for its entire lifetime. Grant table v2 status pages, however, get de-allocated when a guest switched     (back) from v2 to v1. The freeing of such pages requires that the hypervisor know where in the guest these     pages were mapped. The hypervisor tracks only one use within guest space, but racing requests from the     guest to insert mappings of these pages may result in any of them to become mapped in multiple locations.
    Upon switching back from v2 to v1, the guest would then retain access to a page that was freed and perhaps     re-used for other purposes. (CVE-2021-28697)

  - long running loops in grant table handling In order to properly monitor resource use, Xen maintains     information on the grant mappings a domain may create to map grants offered by other domains. In the     process of carrying out certain actions, Xen would iterate over all such entries, including ones which     aren't in use anymore and some which may have been created but never used. If the number of entries for a     given domain is large enough, this iterating of the entire table may tie up a CPU for too long, starving     other domains or causing issues in the hypervisor itself. Note that a domain may map its own grants, i.e.
    there is no need for multiple domains to be involved here. A pair of cooperating guests may, however,     cause the effects to be more severe. (CVE-2021-28698)

  - inadequate grant-v2 status frames array bounds check The v2 grant table interface separates grant     attributes from grant status. That is, when operating in this mode, a guest has two tables. As a result,     guests also need to be able to retrieve the addresses that the new status tracking table can be accessed     through. For 32-bit guests on x86, translation of requests has to occur because the interface structure     layouts commonly differ between 32- and 64-bit. The translation of the request to obtain the frame numbers     of the grant status table involves translating the resulting array of frame numbers. Since the space used     to carry out the translation is limited, the translation layer tells the core function the capacity of the     array within translation space. Unfortunately the core function then only enforces array bounds to be     below 8 times the specified value, and would write past the available space if enough frame numbers needed     storing. (CVE-2021-28699)

  - xen/arm: No memory limit for dom0less domUs The dom0less feature allows an administrator to create     multiple unprivileged domains directly from Xen. Unfortunately, the memory limit from them is not set.
    This allow a domain to allocate memory beyond what an administrator originally configured.
    (CVE-2021-28700)

  - Another race in XENMAPSPACE_grant_table handling Guests are permitted access to certain Xen-owned pages of     memory. The majority of such pages remain allocated / associated with a guest for its entire lifetime.
    Grant table v2 status pages, however, are de-allocated when a guest switches (back) from v2 to v1. Freeing     such pages requires that the hypervisor enforce that no parallel request can result in the addition of a     mapping of such a page to a guest. That enforcement was missing, allowing guests to retain access to pages     that were freed and perhaps re-used for other purposes. Unfortunately, when XSA-379 was being prepared,     this similar issue was not noticed. (CVE-2021-28701)

  - PCI devices with RMRRs not deassigned correctly Certain PCI devices in a system might be assigned Reserved     Memory Regions (specified via Reserved Memory Region Reporting, RMRR). These are typically used for     platform tasks such as legacy USB emulation. If such a device is passed through to a guest, then on guest     shutdown the device is not properly deassigned. The IOMMU configuration for these devices which are not     properly deassigned ends up pointing to a freed data structure, including the IO Pagetables. Subsequent     DMA or interrupts from the device will have unpredictable behaviour, ranging from IOMMU faults to memory     corruption. (CVE-2021-28702)

  - certain VT-d IOMMUs may not work in shared page table mode For efficiency reasons, address translation     control structures (page tables) may (and, on suitable hardware, by default will) be shared between CPUs,     for second-level translation (EPT), and IOMMUs. These page tables are presently set up to always be 4     levels deep. However, an IOMMU may require the use of just 3 page table levels. In such a configuration     the lop level table needs to be stripped before inserting the root table's address into the hardware     pagetable base register. When sharing page tables, Xen erroneously skipped this stripping. Consequently,     the guest is able to write to leaf page table entries. (CVE-2021-28710)

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - arm: guest_physmap_remove_page not removing the p2m mappings The functions to remove one or more entries     from a guest p2m pagetable on Arm (p2m_remove_mapping, guest_physmap_remove_page, and p2m_set_entry with     mfn set to INVALID_MFN) do not actually clear the pagetable entry if the entry doesn't have the valid bit     set. It is possible to have a valid pagetable entry without the valid bit set when a guest operating     system uses set/way cache maintenance instructions. For instance, a guest issuing a set/way cache     maintenance instruction, then calling the XENMEM_decrease_reservation hypercall to give back memory pages     to Xen, might be able to retain access to those pages even after Xen started reusing them for other     purposes. (CVE-2022-23033)

  - A PV guest could DoS Xen while unmapping a grant To address XSA-380, reference counting was introduced for     grant mappings for the case where a PV guest would have the IOMMU enabled. PV guests can request two forms     of mappings. When both are in use for any individual mapping, unmapping of such a mapping can be requested     in two steps. The reference count for such a mapping would then mistakenly be decremented twice. Underflow     of the counters gets detected, resulting in the triggering of a hypervisor bug check. (CVE-2022-23034)

  - Insufficient cleanup of passed-through device IRQs The management of IRQs associated with physical devices     exposed to x86 HVM guests involves an iterative operation in particular when cleaning up after the guest's     use of the device. In the case where an interrupt is not quiescent yet at the time this cleanup gets     invoked, the cleanup attempt may be scheduled to be retried. When multiple interrupts are involved, this     scheduling of a retry may get erroneously skipped. At the same time pointers may get cleared (resulting in     a de-reference of NULL) and freed (resulting in a use-after-free), while other code would continue to     assume them to be valid. (CVE-2022-23035)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES12 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2574-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLED15 / SLED_SAP15 / SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2597-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLED15 / SLED_SAP15 / SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2599-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2601-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2591-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2600-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES12 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2569-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES12 / SLES_SAP12 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2560-1 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution     under certain microarchitecture-dependent conditions. (CVE-2022-29900)

  - insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels     unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was     moved inside a function in Xen. This code movement missed a variable changing meaning / value between old     and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition,     omitting flushes where such are necessary. (CVE-2022-33745)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote Debian 11 host has packages installed that are affected by multiple vulnerabilities as referenced in the dsa-5184 advisory.

  - Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated     user to potentially enable information disclosure via local access. (CVE-2022-21123)

  - Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21125)

  - Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an     authenticated user to potentially enable information disclosure via local access. (CVE-2022-21166)

  - Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially     leading to information disclosure. (CVE-2022-23825)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

  - AMD microprocessor families 15h to 18h are affected by a new Spectre variant that is able to bypass their     retpoline mitigation in the kernel to leak arbitrary data. An attacker with unprivileged user access can     hijack return instructions to achieve arbitrary speculative code execution under certain     microarchitecture-dependent conditions. (CVE-2022-29900)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLED15 / SLED_SAP15 / SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2296-1 advisory.

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2164-1 advisory.

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2158-1 advisory.

  - Racy interactions between dirty vram tracking and paging log dirty hypercalls Activation of log dirty mode     done by XEN_DMOP_track_dirty_vram (was named HVMOP_track_dirty_vram before Xen 4.9) is racy with ongoing     log dirty hypercalls. A suitably timed call to XEN_DMOP_track_dirty_vram can enable log dirty while     another CPU is still in the process of tearing down the structures related to a previously enabled log     dirty mode (XEN_DOMCTL_SHADOW_OP_OFF). This is due to lack of mutually exclusive locking between both     operations and can lead to entries being added in already freed slots, resulting in a memory leak.
    (CVE-2022-26356)

  - race in VT-d domain ID cleanup Xen domain IDs are up to 15 bits wide. VT-d hardware may allow for only     less than 15 bits to hold a domain ID associating a physical device with a particular domain. Therefore     internally Xen domain IDs are mapped to the smaller value range. The cleaning up of the housekeeping     structures has a race, allowing for VT-d domain IDs to be leaked and flushes to be bypassed.
    (CVE-2022-26357)

  - IOMMU: RMRR (VT-d) and unity map (AMD-Vi) handling issues T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Certain PCI devices in a     system might be assigned Reserved Memory Regions (specified via Reserved Memory Region Reporting, RMRR)     for Intel VT-d or Unity Mapping ranges for AMD-Vi. These are typically used for platform tasks such as     legacy USB emulation. Since the precise purpose of these regions is unknown, once a device associated with     such a region is active, the mappings of these regions need to remain continuouly accessible by the     device. This requirement has been violated. Subsequent DMA or interrupts from the device may have     unpredictable behaviour, ranging from IOMMU faults to memory corruption. (CVE-2022-26358, CVE-2022-26359,     CVE-2022-26360, CVE-2022-26361)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLES12 / SLES_SAP12 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2084-1 advisory.

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

The remote SUSE Linux SLED15 / SLED_SAP15 / SLES15 / SLES_SAP15 host has packages installed that are affected by multiple vulnerabilities as referenced in the SUSE-SU-2022:2065-1 advisory.

  - IOMMU: RMRR (VT-d) and unity map (AMD-Vi) handling issues T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Certain PCI devices in a     system might be assigned Reserved Memory Regions (specified via Reserved Memory Region Reporting, RMRR)     for Intel VT-d or Unity Mapping ranges for AMD-Vi. These are typically used for platform tasks such as     legacy USB emulation. Since the precise purpose of these regions is unknown, once a device associated with     such a region is active, the mappings of these regions need to remain continuouly accessible by the     device. This requirement has been violated. Subsequent DMA or interrupts from the device may have     unpredictable behaviour, ranging from IOMMU faults to memory corruption. (CVE-2022-26358, CVE-2022-26359,     CVE-2022-26360, CVE-2022-26361)

  - x86 pv: Race condition in typeref acquisition Xen maintains a type reference count for pages, in addition     to a regular reference count. This scheme is used to maintain invariants required for Xen's safety, e.g.
    PV guests may not have direct writeable access to pagetables; updates need auditing by Xen. Unfortunately,     the logic for acquiring a type reference has a race condition, whereby a safely TLB flush is issued too     early and creates a window where the guest can re-establish the read/write mapping before writeability is     prohibited. (CVE-2022-26362)

  - x86 pv: Insufficient care with non-coherent mappings T[his CNA information record relates to multiple     CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Xen maintains a type     reference count for pages, in addition to a regular reference count. This scheme is used to maintain     invariants required for Xen's safety, e.g. PV guests may not have direct writeable access to pagetables;
    updates need auditing by Xen. Unfortunately, Xen's safety logic doesn't account for CPU-induced cache non-     coherency; cases where the CPU can cause the content of the cache to be different to the content in main     memory. In such cases, Xen's safety logic can incorrectly conclude that the contents of a page is safe.
    (CVE-2022-26363, CVE-2022-26364)

Note that Nessus has not tested for these issues but has instead relied only on the application's self-reported version number.

ID	Name	Product	Family	Severity
164116	GLSA-202208-23 : Xen: Multiple Vulnerabilities	Nessus	Gentoo Local Security Checks	high
163720	SUSE SLES12 Security Update : xen (SUSE-SU-2022:2574-1)	Nessus	SuSE Local Security Checks	high
163647	SUSE SLED15 / SLES15 Security Update : xen (SUSE-SU-2022:2597-1)	Nessus	SuSE Local Security Checks	high
163645	SUSE SLED15 / SLES15 Security Update : xen (SUSE-SU-2022:2599-1)	Nessus	SuSE Local Security Checks	high
163641	SUSE SLES15 Security Update : xen (SUSE-SU-2022:2601-1)	Nessus	SuSE Local Security Checks	high
163640	SUSE SLES15 Security Update : xen (SUSE-SU-2022:2591-1)	Nessus	SuSE Local Security Checks	high
163638	SUSE SLES15 Security Update : xen (SUSE-SU-2022:2600-1)	Nessus	SuSE Local Security Checks	high
163510	SUSE SLES12 Security Update : xen (SUSE-SU-2022:2569-1)	Nessus	SuSE Local Security Checks	high
163507	SUSE SLES12 Security Update : xen (SUSE-SU-2022:2560-1)	Nessus	SuSE Local Security Checks	high
163265	Debian DSA-5184-1 : xen - security update	Nessus	Debian Local Security Checks	medium
162940	SUSE SLED15 / SLES15 Security Update : xen (SUSE-SU-2022:2296-1)	Nessus	SuSE Local Security Checks	medium
162522	SUSE SLES15 Security Update : xen (SUSE-SU-2022:2164-1)	Nessus	SuSE Local Security Checks	medium
162521	SUSE SLES15 Security Update : xen (SUSE-SU-2022:2158-1)	Nessus	SuSE Local Security Checks	high
162240	SUSE SLES12 Security Update : xen (SUSE-SU-2022:2084-1)	Nessus	SuSE Local Security Checks	medium
162183	SUSE SLED15 / SLES15 Security Update : xen (SUSE-SU-2022:2065-1)	Nessus	SuSE Local Security Checks	high

Detections

Analytics

CVE-2022-26362

medium

Tenable Plugins

high

high

high

high

high

high

high

high

high

medium

medium

medium

high

medium

high